1. Field of the Invention
The present invention relates to a technique for the interfacing of a circuit simulation unit and a circuit testing unit, and more particularly, to streamlining circuit simulation output into data for an automated circuit testing program of a circuit testing device.
2. Description of the Background Art
Currently there is a use of automatic test stations (ie., CASS for consolidated automatic support system test stations) to test electronic circuitry found in many different devices such as avionic devices. The test station hosts a digital test instrument such as the L200 by TERADYNE to handle all of the digital device testing. Digital test developers must use a high-level program (ie., LASAR) to create generic test vectors for very complex digital circuits. LASAR is a digital circuit simulator (program) with fault simulation capability. A test engineer will develop models of a digital circuit using LASAR, provide it with stimulus which he wants to inject into the board, then debug and analyze the circuit using LASAR's screen output capability. Once the test stimuli are performing correctly, the developer will use LASAR to simulate real world fault conditions. LASAR will then create “snapshots” of these fault conditions which can be compared to fault-free output following a real world test. These snap-shots are to be collected into a file, much like a database, called a fault dictionary. The fault dictionary must be tailored for the particular tester that will be used to test the digital board.
The CASS test station is equipped with an instrument called the DTU (Digital Test Unit). It is the instrument which tests digital circuitry. While the CASS, in general, uses ATLAS, the DTU has its own unique language called L200. Digital test code must be written in the L200 language to be used at run-time by the CASS test station. Some method is needed to convert LASAR output to L200 test code.
The standard method to generate a complete L200 test job for CASS using LASAR output is cumbersome, unwieldy, and is a path fraught with error. Test vectors generated are anything but readable, even on jobs with a small number of patterns, because only pin state changes are shown. The method does not work very well with hierarchical model design such as one would employ to test a box, an Interface Device (ID), for example. Often the test engineer needs to build two or more nets and combine them into one large model. LASAR permits this feature but post-processing into L200 is difficult if not prohibitive. The L200 post-processor does not allow names of chips to exceed four characters which precludes the use of scoping type fault callouts required by hierarchical modeling.
Furthermore, the standard 9-9-1 mismatch scoring algorithm is simply not adequate in some situations. The 9-9-1 weighting factor method of mismatch scoring sometimes punishes the real fault signature too severely by overlooking valid matches. A typical 9-9-1 mismatch scoring fault analyzer had much difficulty producing accurate fault callouts for the signatures represented in the fault dictionary. Some of the faults were totally erroneous and directed the technician to replace many good components while never touching the actual faulty one. Apparently, the correct fault signature was scored for mismatch too punitively. Analysis revealed that the correct POPATs (primary output patterns) found were not given adequate credit. Furthermore, the 9-9-1 method has great difficulty handling anomalies such as multiple faults or poor initialization.